Dielectric cure for reducing oxygen vacancies

ABSTRACT

A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

This application is a divisional of U.S. patent application Ser. No.09/326,429, filed on Jun. 4, 1999, now U.S. Pat. No. 6,281,142.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits. Inparticular, the invention relates to dielectrics with reduced oxygenvacancies and methods of providing the same.

BACKGROUND OF THE INVENTION

Manufacturers of integrated circuits are continually increasing circuitdensity in pursuit of faster processing speeds and lower powerconsumption. As the packing density of memory cells continues toincrease, components such as capacitors must still maintain a certainminimum charge storage to ensure reliable operation of the memory cell.It is thus increasingly important that capacitors achieve a high storedcharge per footprint or unit of chip area occupied.

Several techniques increase the total charge capacity of the cellcapacitor without significantly affecting the chip area occupied by thecell. One technique is to use dielectric materials having higherdielectric constants (k). Such materials include tantalum pentoxide(Ta₂O₅), barium strontium titanate (BST), strontium titanate (ST),barium titanate (BT), lead zirconium titanate (PZT), and strontiumbismuth tantalate (SBT). Using such materials enables the creation ofmuch smaller and simpler capacitor structures for a given stored chargerequirement, enabling the packing density dictated by future circuitdesign.

Manufacturers, however, have encountered difficulties in incorporatingthese materials into the fabrication process because materials withhigher dielectric constants often develop defects associated with oxygenvacancies (missing oxygen atoms in the crystal lattice). For example,when depositing barium strontium titanate, the barium strontium titanatecan have missing oxygen atoms that may deform its crystalline structureand yield poor dielectric properties.

To reduce the oxygen vacancies, manufacturers often subject dielectricmaterials to re-oxidation anneals after their depositions. Conventionalre-oxidation anneals typically heat the integrated circuit in anoxidizing environment. Ordinarily, such a process is highly oxidizingand can thus degrade other substances in the integrated circuit. Forexample, a re-oxidation anneal can degrade materials used in capacitorplates, electrodes, conductive plugs, the silicon substrate and thelike. Such degradation can reduce the reliability of these electricalelements, and has been viewed as a significant obstacle to incorporatinghigh dielectric materials into integrated circuits. Indeed, in someinstances, manufacturers have added protective barrier layers to reducethe degradation thereby further increasing costs and fabricationcomplexity. Such protective barrier layers may exist, for example,between a bottom electrode material and a polysilicon plug.

SUMMARY OF THE INVENTION

A unique electrochemical process fills oxygen vacancies in dielectricswhile reducing oxidation of nearby electrodes and conductors. Forexample, in one embodiment, an electromagnetic field moves oxygenvacancies to the surface of a dielectric film. Annihilation of oxygenvacancies can then be realized by an oxidizing treatment while theelectromagnetic field continues to be applied. That is, the oxygentreatment removes the oxygen vacancies as the electromagnetic fielddirects the oxygen vacancy towards the surface of the dielectric film.The oxygen treatment can include ozone (O₃), nitrous oxide (N₂O), oxygen(O₂), or the like.

In one embodiment, a unique plasma treatment provides the oxygen ionsthat react with the oxygen vacancies. In another embodiment, a uniqueelectrolysis treatment provides the oxygen ions that react with theoxygen vacancies.

Another embodiment of the invention relates to a method of reducingoxygen vacancies in a high dielectric constant capacitor. The methodcomprises depositing a first electrode on a semiconductor substrate anddepositing a high constant dielectric above the first electrode. Thehigh constant dielectric has a plurality of oxygen vacancies therein.The method further comprises applying an electrical bias to the highconstant dielectric wherein the appropriate polarity of the electricalbias causes the oxygen vacancies to migrate towards the surface of thehigh constant dielectric. The method further comprises plasma treatingthe high constant dielectric with a plurality of oxygen ions at atemperature below 500° Celsius (C.) wherein the oxygen ions fill atleast a portion of the oxygen vacancies from the high constantdielectric.

An additional embodiment of the invention relates to a method ofreducing oxygen vacancies in a dielectric. The method comprises applyingan electromagnetic field to a dielectric to cause oxygen vacancies inthe dielectric to migrate towards the surface of the dielectric andplasma treating the dielectric with oxygen ions which react with atleast a portion of the oxygen vacancies in the dielectric.

Yet another embodiment of the invention relates to a method of reducingoxygen vacancies in a memory cell. The method comprises depositing afirst electrode over a portion of a poly plug and depositing adielectric over the first electrode. The dielectric has a plurality ofoxygen vacancies therein. The method further comprises applying anelectromagnetic field that causes the oxygen vacancies in the dielectricto migrate. The method further comprises plasma treating the dielectricwith a plurality of oxygen ions wherein at least a portion of the oxygenions react with the oxygen vacancies in the dielectric. The methodfurther comprises depositing a second electrode over at least a portionof the dielectric.

One embodiment relates to a method of reducing oxygen vacancies in ametal-insulator-metal structure. The method comprises depositing a firstmetal electrode over a substrate and depositing a dielectric over thefirst metal electrode. The dielectric has a plurality of oxygenvacancies therein. The method further comprises applying anelectromagnetic field that causes the oxygen vacancies in the dielectricto migrate and plasma treating the dielectric with a plurality of oxygenions wherein at least a portion of oxygen ions fill oxygen vacancies inthe dielectric. The method further comprises depositing a second metalelectrode over the dielectric.

Another embodiment relates to a method of reducing oxygen vacancies in adielectric on a semiconductor surface. The method comprises depositingon a semiconductor substrate, a high constant dielectric. The highconstant dielectric has a plurality of oxygen vacancies therein. Themethod further comprises applying an electromagnetic field to thedielectric wherein the electromagnetic field causes the oxygen vacanciesin the high constant dielectric to migrate towards the surface of thehigh constant dielectric. The method further comprising applying anelectrolytic solution to the high constant dielectric wherein theelectrolytic solution comprises at least a portion of oxygen ions thatreact with the oxygen vacancies to thereby fill a portion of the oxygenvacancies from the high constant dielectric.

An additional embodiment relates to a method of reducing oxygenvacancies in a dielectric. The method comprises applying anelectromagnetic field to a dielectric to cause oxygen vacancies in thedielectric to migrate towards the surface of the dielectric and applyingan electrolytic solution to the dielectric wherein oxygen ions in theelectrolytic solution react with at least a portion of the oxygenvacancies in the dielectric.

Yet another embodiment relates to a method of reducing oxygen vacanciesin a memory cell. The method comprises depositing a first electrode overa portion of a semiconductor transistor structure and depositing adielectric over the first electrode. The dielectric has a plurality ofoxygen vacancies therein. The method further comprises applying anelectromagnetic field that causes the oxygen vacancies in the dielectricto migrate and subjecting the dielectric to electrolysis wherein oxygenions react with the oxygen vacancies in the dielectric. The methodfurther comprises depositing a second electrode over the dielectric.

One embodiment of the invention relates to a method of reducing oxygenvacancies in a metal-insulator-metal structure. The method comprisesdepositing a first metal electrode over a substrate and depositing adielectric over the first metal electrode. The dielectric has aplurality of oxygen vacancies therein. The method further comprisingapplying an electromagnetic field that causes the oxygen vacancies inthe dielectric to migrate and subjecting the dielectric to electrolysiswherein oxygen ions react with at least a portion of the oxygenvacancies in the dielectric. The method further comprises depositing asecond metal electrode over the dielectric.

Another embodiment of the invention relates to a method of reducingoxygen vacancies in a dielectric. The method comprising applying anelectromagnetic field to a dielectric having oxygen vacancies therein.The method further comprises applying an electrolytic solution to thedielectric wherein oxygen ions in the electrolytic solution react withat least a portion of the oxygen vacancies in the dielectric.

Yet another embodiment of the invention relates to a method of reducingoxygen vacancies in a dielectric. The method comprises applying anelectromagnetic field to a dielectric to cause oxygen vacancies in thedielectric to migrate. The method further comprises applying oxygen ionsto the surface of the dielectric wherein the oxygen ions react with themigrating oxygen vacancies.

One embodiment of the invention relates to semiconductor structure thatcomprises a poly plug substantially free of oxidation and a firstelectrode above at least a portion of the poly plug. The semiconductorstructure further comprises a dielectric layer above at least a portionof the first electrode wherein the dielectric layer has a highdielectric constant. The semiconductor structure further comprises asecond electrode above at least a portion of the dielectric layer.

Another embodiment relates to a memory cell that comprises a poly plugsubstantially free of oxidation and a first electrode above at least aportion of the poly plug. The memory cell further comprises a dielectriclayer above at least a portion of the first electrode, the dielectriclayer having a high dielectric constant. The memory cell furthercomprises a second electrode above at least a portion of the dielectriclayer.

An additional embodiment relates to a metal-insulator-metal structurethat comprises a first metal layer substantially free of oxidation and adielectric layer above the first metal layer. The dielectric layer has ahigh dielectric constant. The metal-insulator-metal structure furthercomprising a second metal layer above the dielectric layer.

Another aspect of the invention relates to a method of reducing oxygenvacancies comprising applying an electromagnetic field that causes theoxygen vacancies in a material to migrate; and reducing the amount ofoxygen vacancies by subjecting the material to an oxidizing treatment.

For purposes of summarizing the invention, certain aspects advantagesand novel features of the invention are described herein. It is to beunderstood that not necessarily all such advantages may be achieved inaccordance with any particular embodiment of the invention. Thus, forexample, those skilled in the art will recognize that the invention maybe embodied or carried out in a manner that achieves one advantage orgroup of advantages as taught herein without necessarily achieving otheradvantages as may be taught or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects, advantages, and novel features of the inventionwill become apparent upon reading the following detailed description andupon reference to the accompanying drawings. The present invention isdescribed in more detail below in connection with the attached drawings,in which:

FIG. 1 is a schematic cross-section of one embodiment of a partiallyfabricated memory cell.

FIG. 2 is a schematic cross-section of one embodiment of ametal-insulator-semiconductor structure.

FIG. 3 shows the memory cell of FIG. 1, incorporating themetal-insulator-semiconductor structure of FIG. 2 with an overlyingdielectric.

FIG. 4 is a schematic cross-section of another embodiment of a partiallyfabricated memory cell with a roughened surface.

FIG. 5 is a schematic cross-section of an embodiment of ametal-insulator-metal semiconductor structure.

FIG. 6 shows a wafer subjected to an electromagnetic field in oneembodiment of the invention.

FIG. 7 shows a wafer subjected to electrolysis in accordance with oneembodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

While illustrated in the context of a dynamic random access memory(DRAM) cell, embodiments of the invention can be used to improve a widerange of products and processes. For example, the invention can be usedto improve materials with high dielectric constants,metal-oxide-semiconductor structures, metal-oxide-metal structures andthe like.

FIG. 1 illustrates a partially fabricated memory cell 4 formed withinand over a semiconductor substrate 10, in accordance with one embodimentof the present invention. While the illustrated substrate 10 comprisesan intrinsically doped monocrystalline silicon wafer, it will beunderstood by one of skill in the art of semiconductor fabrication thatthe “substrate” in other arrangements can comprise other forms ofsemiconductor layers which include active or operable portions ofsemiconductor devices.

A plurality of transistor gate electrodes 12 overlie the substrate 10,adjacent transistor active areas 14 within the substrate 10. It will beunderstood that several transistors are formed across a memory arraywithin a DRAM circuit or chip. Field oxide elements 16 isolate theactive areas 14 of different transistors. In one embodiment, the widthof the gates are preferably less than about 0.25 microns (μm).

A first insulating layer 18 is shown covering the gate electrodes 12.Generally, this insulating layer 18 comprises a form of oxide, such asborophosphosilicate glass (BPSG). Depending upon the presence or absenceof other circuit elements, the first insulating layer 18 typically has athickness between about 0.5 μm to 1.0 μm. For example, certain DRAMcircuit designs called for “buried” digit lines running below the cellcapacitors, such that a thicker insulating layer is required toelectrically isolated the digit line from the underlying transistors andthe overlying capacitors.

A conductive contact 20 is shown extending through the first insulatinglayer 18 to electrically contact an active area 14 between gateelectrodes. In the illustrated embodiment, the material comprisesconductively doped polycrystalline silicon or polysilicon, whichadvantageously can be deposited into deep, narrow contact vias with goodstep coverage by chemical vapor deposition (CVD). In accordance withindustry terminology, the conductive contact shall be referred to as a“poly plug” 20. In another embodiment, the poly plug 20 can include avariety of conductors including tungsten (W), aluminum (Al) or the like.As described in further detail below, the poly plug 20 is substantiallyfree of oxidation that occurs when removing oxygen vacancies from thememory cell 4.

The barrier layer 32 advantageously acts as a diffusion barrier toreduce oxidation of the underlying poly plug 20 and to reduce silicondiffusion of the bottom electrode or dielectric discussed in furtherdetail below. The barrier layer 32 may comprise stoichiometric nitride(Si₃N₄), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride(TaSiN), titanium nitride (TiN), titanium aluminum nitride (TiAlN),titanium silicon nitride (TiSiN), tungsten nitride (WN_(x)), tungstensilicon nitride (WSiN), silicon nitride (SiN), molybdenum (Mo) or thelike. However, the skilled artisan will recognize that a wide range ofmaterials can be used to form the barrier layer 32.

The barrier layer 32 can be formed by nitridizing the poly plug 20 or bychemical vapor deposition (CVD), metal organic chemical vapor deposition(MOCVD), low temperature sputtering or the like. In one embodiment, thebarrier layer 32 is approximately 10 angstroms (Å) to approximately 1000or more angstroms (Å) thick. In certain other embodiments, the barrierlayer 32 is not used.

A structural layer 22 is then formed over the first insulating layer 18and the barrier layer 32. As will be better understood from the methodsdescribed below, this structural layer 22 need not become a permanentpart of the circuit. Accordingly, the skilled artisan has a great dealof flexibility in the selection of this material. Preferably, thestructural layer 22 is selectively etchable relative to the underlyingfirst insulating layer 18. In one embodiment, the structural layer 22 isBPSG. The surface area and thus the capacitance of the memory cell 4 isinfluenced by the thickness of the structural layer 22. For theillustrated circuit, using 0.25 μm resolution, the structural layer 22preferably has a thickness of greater than about 1.0 μm, more preferablybetween about 1.0 μm and 2.0 μm.

A via 24 is formed in the structural layer 22 to expose the underlyingpoly plug 20, and a conductive layer 26 deposited over the structurallayer 22 and into the via 24 to make electrical contact with the polyplug 20. The top of the structural layer 22, and the portion of theconductive layer 26 overlying the structural layer 22, can then beplanarized to leave the conductive layer 26 isolated within the via 24,as shown in FIG. 1. Such planarization can be accomplished by mechanicalabrasion, preferably chemically aided by etchants in a slurry in achemical mechanical planarization or polishing (CMP) process.

The conductive layer 26 serves as the bottom or reference electrode ofthe memory cell 4, and can comprise a conductively doped polysilicon,hemispherical grain (HSG) polysilicon, platinum (Pt), ruthenium (Ru),ruthenium oxide (RuO_(x)), iridium (Ir), iridium oxide (IrO_(x)),palladium (Pd), tungsten (W) tungsten nitride (WN_(x)), tantalum nitride(TaN), titanium nitride (TiN), titanium oxygen nitride (TiON) or thelike. The illustrated conductive layer 26 thus takes on athree-dimensional folding shape that is of greater surface area than thearea of the substrate 10 which the memory cell 4 occupies. Other methodsof increasing surface area can include creating a rough surface on theconductive layer 26, or creating multiple concentric container shapesfor one memory cell. The skilled artisan will find application for theprocesses and materials discussed below for any of a number of capacitorconfigurations.

The conductive layer 26 can be deposited by chemical vapor deposition(CVD), Low Pressure Chemical Vapor Deposition (LPCVD), metal organicchemical vapor deposition (MOCVD), plasma enhanced chemical vapordeposition (PECVD) or the like. While the thickness of the conductivelayer 26 is approximately 100 angstroms (Å) to approximately 1000 (Å),the skilled artisan will recognize that the thickness of the conductivelayer 26 can vary over a wide variety of ranges.

FIG. 2 illustrates a capacitor comprising ametal-insulator-semiconductor structure 30. Themetal-insulator-semiconductor structure 30 comprises the conductivelayer 26, a dielectric 34, and a second conductive layer 36. Theconductive layer 26 is hereinafter referred to as the bottom electrode26. In certain embodiments, the barrier layer 32 may exist between thedielectric 34 and the bottom electrode 26. In yet other embodiments, afirst barrier layer 32 may exist between the dielectric 34 and thebottom electrode 26, and a second barrier layer 32 may exist between thebottom electrode 26 and the poly plug 20. In certain other embodiments,the barrier layer 32 is not used.

The dielectric 34 is an insulator that provides electrical insulation.In one embodiment of the invention, the dielectric 34 is a conventionaldielectric material such as silicon dioxide or silicon nitride. Inanother embodiment, the dielectric 34 is a material with a highdielectric constant. Materials having high dielectric constants greaterthan 20 are to be distinguished from conventional dielectric materialssuch as silicon dioxide which as a dielectric constant of approximately3.9. The high constant dielectric materials typically comprise inorganicnon-metallic oxides such as tantalum pentoxide (Ta₂O₅) oxideparaelectric materials, and ferroelectric materials including by way ofexample, barium strontium titanate ((BaSr)TiO₃ or BST), strontiumtitanate (ST), barium titanate (BT), lead zirconium titanate (PZT),strontium bismuth tantalate (SBT), or the like.

In one embodiment, the dielectric 34 is deposited by direct current (DC)magnetron sputtering at a temperature range of approximately 200° C. toapproximately 800° C. A target material can comprise a stoichiometriccomposition of powered materials. The thickness of such a dielectriclayer is preferably in the range of approximately 20 Å to approximately2,500 Å thick. Other deposition techniques such as CVD, LPCVD, PECVD orMOCVD can be utilized. For example, in one embodiment, the dielectric 34comprises tantalum pentoxide and is between approximately 40 Å andapproximately 100 Å thick. Preferably, the tantalum pentoxide isapproximately 60 Å thick. The dielectric constant (k) of tantalumpentoxide is 25 to 50, and when doped with silicon can increase up to130. As is known in the art, tantalum pentoxide can be formed bychemical vapor deposition, using an organometallic precursor.

In another embodiment, the dielectric 34 comprises barium strontiumtitanate that is between approximately 100 Å and approximately 1000 Åthick. Preferably, the barium strontium titanate is approximately 200 Åto approximately 300 Å thick. While the dielectric constant (k) of thebarium strontium titanate varies from about 100 to 600, depending uponthe phase and thickness of the material, the preferred dielectric 34 hasa dielectric constant of about 300. As is known in the art, bariumstrontium titanate is preferably deposited by chemical vapor depositiontechniques comprising reacting volatile complexes containing barium(Ba), strontium (Sr) and titanium (Ti) in an oxygen ambient.

During the deposition of the dielectric 34, oxygen vacancies oftendevelop wherein oxygen atoms are missing in the crystal lattice of thedielectric 34. For example, the tantalum pentoxide or barium strontiumtitanate may contain defects where missing oxygen atoms deform theircrystalline structures and yield poor dielectric properties such aslower dielectric constants and higher leakage. As explained in moredetail below, one embodiment of the invention reduces the oxygenvacancies in the dielectric 34 by subjecting the dielectric 34 to anelectromagnetic field and a plasma treatment at relatively lowtemperatures. Another embodiment of the invention subjects thedielectric 34 to an electromagnetic field and electrolysis at relativelylow temperatures. Thereafter, the deposited amorphous dielectric 34 canbe converted to a crystalline phase during a relatively quickhigh-temperature, non-oxidizing reflow that does not significantlydegrade the poly plug 20, the barrier layer 32 and/or the bottomelectrode 26.

After depositing and treating the dielectric 34, the second conductivelayer 36 is deposited over the dielectric 34. The second conductivelayer 36 typically comprises platinum (Pt), ruthenium (Ru), rutheniumoxide (RuO_(x)), iridium (Ir), iridium oxide (IrO_(x)), palladium (Pd),tungsten (W), tungsten nitride (WN), tantalum nitride (TaN), titaniumnitride (TiN), titanium oxygen nitride (TiON), or the like. A suitabledeposition process is sputtering, CVD, LPCVD, PECVD, MOCVD or the like.The second conductive layer 36 is preferably deposited to a thicknessrange of approximately 100 Å to approximately 2000 Å.

With reference now to FIG. 3, the memory cell 4 is shown with acompleted capacitor structure. A third conductive layer 38 may existabove the second conductive layer 36, preferably the third conductivelayer 38 forms a part of the top electrode. Exemplary materials for thethird conductive layer 38 include polysilicon, tungsten.

An interlevel dielectric (ILD) 40 has also been formed over the secondconductive layer 36. Typically, the ILD 40 comprises a form of oxide,such as borophosphosilicate glass (BPSG). Deposition of the BPSG isfollowed by a reflow anneal step for better step coverage and avoidingkeyholes, as well as to densify the layer. The reflow is conducted byheating the wafer to temperatures of approximately 900° C. to 1000° C.If not separately annealed before this point, the deposited amorphousdielectric 34 can be converted to a crystalline phase during this hightemperature reflow. Although not shown, the skilled artisan willappreciate that contacts are created through the BPSG 40 to connect thetop electrode 36, 38 to wiring formed above or within the BPSG 40.

FIG. 4 illustrates another embodiment of memory cell 4 made inaccordance with an, embodiment of the invention. As discussed withrespect to FIG. 1, the memory cell 4 comprises the semiconductorsubstrate 10, the plurality of transistor gate electrodes 12, theadjacent transistor active areas 14, the field oxide elements 16, thefirst insulating layer 18 and the “poly plug” 20. A structural layer 22is then formed over the first insulating layer 18. A via 24 is formed inthe structural layer 22 to expose the underlying poly plug 20.

The bottom electrode 26 includes a rugged or rough silicon layer 28. Therough silicon layer 28 enhances the surface area of the bottom electrode26. The rough silicon layer 28 typically comprises hemispherical grained(HSG) silicon or HSG polysilicon. The rough silicon layer 28 may beformed by a number of different methods, including gas phase nucleationand surface seeding.

The barrier layer 32, and the dielectric 34 are then layered upon therough surface of the bottom electrode 26. The barrier layer 32 comprisesthe substances discussed above. For example, when tantalum pentoxide isused as the dielectric 34, a nitrided poly surface may be used as thebarrier layer 32.

The dielectric 34 is typically coated with the second conductive layer36 to form a metal-insulator-semiconductor structure. The barrier layer32 advantageously acts as a diffusion barrier to reduce oxidation of theunderlying bottom electrode 26. For example, the poly oxidation isreduced by the nitride barrier layer 32.

The dielectric 34 is a material with a high dielectric constant whereinthe oxygen vacancies in the dielectric 34 have been reduced with anelectromagnetic field. In another embodiment, the invention reduces theoxygen vacancies in the dielectric 34 with a unique electrolysistechnique.

The second conductive layer 36 is then deposited on the dielectric 34.The second conductive layer 36 may comprise titanium nitride (TiN),tantalum nitride (TaN), titanium oxygen nitride (TiON), tungsten (W),tungsten nitride (WN), or the like that is deposited with conventionaltechniques. Also, a third conductive layer may comprise polysilicondeposited with chemical vapor deposition techniques on the secondconductive layer 36. In one embodiment, the second conductive layer 36is deposited by chemical vapor deposition and may have a thickness ofabout 200 to 400 Å.

FIG. 5 illustrates a metal-insulator-metal structure 50. Themetal-insulator-metal structure 50 is hereinafter referred to as the MIM50. The MIM 50 comprises the poly plug 20, the barrier layer 32, thestructural layer 22, a first electrode 54, a dielectric 56, and a secondelectrode 58. The MIM 50 has a wide variety of uses including dynamicrandom access memory capacitor modules, electro-optical devices, liquidcrystal displays, diode structures and the like.

The barrier layer 32 as discussed above, reduces oxidation of the polyplug 20 and reduces silicon diffusion to the first electrode 54 and thedielectric 56. The first electrode 54 comprises iridium (Ir), iridiumoxide (IrO_(x)), ruthenium (Ru), ruthenium oxide (RuO_(x)), tantalum(Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN),titanium oxygen nitride (TiON), tungsten (W), tungsten nitride (WN_(x)),molybdenum (Mo), platinum (Pt), silver (Ag), palladium (Pd) and thelike.

The dielectric 56 comprises a dielectric material such as ployimide,silicon oxynitride, silicon nitride, tantalum pentoxide (Ta₂O₅), bariumstrontium titanate (BST), strontium titanate (ST), barium titanate (BT),lead zirconium titanate (PZT), strontium bismuth tantalate (SBT), or thelike. The second electrode 58, like the first electrode 54, comprisesiridium (Ir), iridium oxide (IrO_(x)), ruthenium (Ru), ruthenium oxide(RuO_(x)), tantalum (Ta), tantalum nitride (TaN), titanium (Ti),titanium nitride (TiN), titanium oxygen nitride (TiON), tungsten (W),tungsten nitride (WN_(x)), molybdenum (Mo), platinum (Pt), silver (Ag),palladium (Pd), or the like.

The amount of charge stored on the capacitor of the memory cell 4 or theMIM 50 is proportional to the capacitance as follows:$C = \frac{ɛ\quad ɛ_{o}A}{d}$

where ∈ is the dielectric constant of the capacitor dielectric, ∈_(o) isthe vacuum permittivity, A is the electrode area, and d represents thespacing between electrodes.

Thus, a dielectric 34 with a high dielectric constant can improvecapacitance. One problem with incorporating dielectrics 34 with highdielectric constants into the memory cell 4 is the degradation that canoccur to the bottom electrode 26 or the poly plug 20. In particular,when the dielectrics 34, 56 undergo conventional re-oxidation to removeoxygen vacancies, the re-oxidation tends to also oxidize the firstelectrode 54, the barrier layer 32, the poly plug 20 or the secondelectrode 58. The oxidation of such layers is undesirable since it has amuch lower dielectric constant and adds in series to the capacitance ofthe dielectrics 34, 56, thus lowering the total capacitance.

Therefore, a thin native oxide layer present on the bottom electrode 26,the first electrode 54, or the poly plug 20, results in a largedegradation in capacitance. Furthermore, even when the bottom electrode26 is made of a noble metal, such as platinum (Pt), the oxygen inconventional re-oxidation processes may diffuse through the platinum,contaminating the underlying poly plug 20.

Reduction of Oxygen Vacancies

As discussed above, the dielectric 34 in the memory cell 4 and thedielectric 56 in the MIM 50 structure often develop defects associatedwith oxygen vacancies (missing oxygen atoms in the crystal lattice).Such oxygen vacancies, however, can result in high leakage currents,lower capacitance, less reliable operation and undesired dielectricproperties. Furthermore, materials with oxygen vacancies are often moreprone to degradation such as resistance degradation.

Oxygen vacancies in high constant dielectric constant materials such asthe dielectric 34 are mobile under certain conditions. The inventionuses this mobility to attract the oxygen vacancies towards the surfaceof the dielectric 34, 56. Once the oxygen vacancies near the surface,oxygen ions in the environment are used to fill the oxygen vacancies.The following reaction represents the presence of oxygen vacancies:

O _(O) ^(X)=½O ₂ +V ^({umlaut over ( )}) _(O)+2 e′

where, in accordance with Kroger-Vink notation, O_(O) ^(X) denotes thelocation of an oxygen vacancy within the crystalline lattice, ½O₂denotes molecular oxygen in a gaseous phase, V^({umlaut over ( )}) _(O)denotes an oxygen vacancy in the crystalline lattice with an effectivecharge of +2 with respect to the perfect crystalline lattice, and e′denotes an electron with an effective charge of −1.

On the other hand, oxygen ion formation can be represented as:

½O ₂+2e′=O″

where, in accordance with Kroger-Vink notation, ½O₂ denotes molecularoxygen in a gaseous phase, e′ denotes an electron with an effectivecharge of −1 and O″ denotes oxygen ions with an effective charge of −2.

Reduction of Oxygen Vacancies with an Electromagnetic Field

To fill the oxygen vacancies, one embodiment of the invention, asillustrated in FIG. 6, uses a unique plasma treatment that subjects thedielectrics 34, 56 to an electric, magnetic or electromagnetic field 60.The electromagnetic field 60 is hereinafter referred to as the bias 60.For example, after the dielectric 34 has been deposited on the barrierlayer 32 or the bottom electrode 26, the dielectric 34 is subjected to abias 60. The bias 60 comprises a magnetic field, a voltage, a current, abias or the like.

Oxygen vacancies in a dielectric 34 are mobile under forces from thebias 60. Depending on the polarity of the bias 60, the oxygen vacanciescan migrate towards or away from an upper surface of the dielectric 34.Thus, when the bias 60 is applied to the dielectrics 34, 56 the oxygenvacancies can migrate to the surface of the dielectrics 34, 56. At thesurface, the oxygen vacancies can be reduced with oxygen ions present inthe environment.

As illustrated in FIG. 6, a radio frequency (RF) power source creates aplasma 66 within a chamber 68. The plasma 66 can comprise any substancethat creates oxygen ions including, but not limited to oxygen (O₂),nitrous oxide (N₂O), ozone (O₃) or the like. A wafer 62 comprising thememory cell 4 or MIM 50 is connected to a positive voltage source 64.Therefore, the wafer 62 has a positive bias 60 relative to the plasma66. The positive bias 60 causes the oxygen vacancies to migrate towardsthe surface of the dielectrics 34, 56. At the surface, the oxygenvacancies combine with the oxygen ions in the plasma 66.

The voltage of the bias 60 can be either positive or negative dependingon the desired direction of the oxygen vacancy migration. Furthermore,the amount of the voltage is tuned for the resistance degradationcharacteristics of the dielectric 34, 56, the type of plasma 66, theenvironmental temperature of the chamber 68, the length of time thewafer 62 is subjected to the plasma treatment, etc. In one embodiment,the amount of the bias 60 is selected based on the number of oxygenvacancies, the temperature of the plasma treatment, the length of timeof the plasma treatment. In one embodiment, the electric field rangesfrom approximately 250 to approximately 2,000 kilovolt per centimeter(kV/cm).

One advantage is that migrating oxygen vacancies with an electric fieldcan significantly decrease the temperature required for re-oxidation. Inone embodiment, the environmental temperature preferably ranges fromapproximately 300° C. to approximately 400° C. during re-oxidation. Inother embodiments, the environmental temperature ranges fromapproximately 20° C. to approximately 500° C. during re-oxidation.

The length of time the bias 60 and the plasma 66 are applied to thewafer 62 can vary depending the desired operating parameters. In oneembodiment, the length of time varies from approximately 20 seconds toapproximately 600 seconds, and is preferably approximately 2 minutes.

Such a plasma treatment can be performed, for example, in a conventionalplasma chamber 68 or conventional in-situ plasma chamber 68. Exemplaryparameters include a chamber pressure from approximately 1 mTorr toapproximately 10 Torr, RF power from approximately 100 W toapproximately 1,500 W. The gas flows from approximately 50 standardcubic centimeters per minute (sccm) to approximately 5000 sccm ofoxygen, nitrous oxide or ozone. The skilled artisan will recognize,however, that each of the above noted parameters can be variedsignificantly and furthermore that different etch chemistries can beused, while still obtaining reduction of the oxygen vacancies.

For example, after the dielectric 34 has been deposited on the bottomelectrode 26, the wafer 62 is subjected to the novel plasma treatment.In one embodiment, an approximately 0.5 volt bias 60 is applied to thewafer 62 for approximately 2 minutes at temperatures ranging from 300°C. to 400° C. In this example, the dielectric 34 is a BST layer that isapproximately 200 Å thick and the plasma 66 comprises oxygen (O₂),nitrous oxide (N₂O), or ozone (O₃). With the bias 60, the oxygenvacancies migrate towards the surface of the dielectric 34 where theycombine with oxygen ions in the plasma 66. The oxygen vacancies in thedielectric. 34 are thereby reduced.

An advantage of one embodiment of the plasma treatment is that theremoval of the oxygen vacancies in the dielectric 34 does notsubstantially oxidize or degrade the poly plug 20. Unlike conventionalhigh-temperature anneals, the oxygen ions in the plasma treatment do notgenerally diffuse through the barrier layer 32 or the bottom electrode26 to significantly oxidize or degrade the poly plug 20. Thus, someembodiments can eliminate the barrier layer 32. For embodiments withoutthe barrier layer 32, the oxygen ions in the plasma treatment do notgenerally diffuse through the bottom electrode to significantly degradeor oxidize the poly plug 20. Thus, after reducing the number of oxygenvacancies in the dielectric 34, the poly plug 20 remains substantiallyfree of oxidation.

The deposited amorphous dielectric 34 can be converted to a crystallinephase during a relatively quick high-temperature, non-oxidizing reflow.For example, the dielectric 34 comprising tantalum pentoxide or BST canbe subjected to a rapid thermal anneal in an nitrogen (N₂) environmentfrom approximately 30 to approximately 60 seconds at temperaturesexceeding 500° C. The rapid thermal anneal reduces the degradation oroxidation that can occur to the poly plug 20. Thereafter, the secondconductive layer 36 is deposited on the dielectric 34.

In another example with the MIM 50, after the dielectric 56 has beendeposited on the first electrode 54, the MIM 50 is subjected to thenovel plasma treatment. The bias 60 is applied to the MIM 50 and theplasma 66 comprises oxygen (O₂), nitrous oxide (N₂O), or ozone (O₃).With the bias 60, the oxygen vacancies migrate towards the surface ofthe dielectric 56 where they combine with oxygen ions in the plasma 66.The oxygen vacancies in the dielectric 56 are thereby reduced.Thereafter, the second electrode 58 is deposited on the dielectric 56.

An advantage of one embodiment of the plasma treatment is that theremoval of the oxygen vacancies in the dielectric 34 does notsubstantially oxidize or degrade the first electrode 54, the barrierlayer 32, and/or the poly plug 20. For example, the oxygen ions in theplasma treatment do not generally diffuse through the dielectric 34 tosignificantly oxidize or degrade the first electrode 54, the barrierlayer 32, and/or the poly plug 20. Thus, after reducing the number ofoxygen vacancies in the dielectric 34, the first electrode 54, thebarrier layer 32 and/or the poly plug 20 remain substantially free ofoxidation.

Another advantage of one embodiment of the invention is that the bias 60is generally uniform throughout the wafer 62. Thus, the bias 60 iseffective at reducing oxygen vacancies in variations on the surface ofthe wafer 62, such as side walls, roughed surfaces, and other threedimensional surfaces.

An additional advantage of one embodiment of the invention is that theenvironmental temperature during the plasma treatment is generally lowerthan in conventional high-temperature approaches exceeding approximately500° C. Reducing oxygen vacancies at temperatures below approximately500° C. in the memory cell 4, reduces oxidation of the bottom electrode26 or the poly plug 20. Likewise, in the MIM 50, reducing oxygenvacancies at lower temperatures reduces the oxidation of the firstelectrode 54, the barrier layer 22 and/or the poly plug 20 in the MIM50.

Because there is less oxidation to the bottom electrode 26, the polyplug 20 or the first electrode 54, the total capacitance is increased.Furthermore, more desirable bottom electrodes 26 and barrier layers 32can be used. For example, a bottom electrode 26 comprising nitrided HSGpolysilicon can retain its permittivity of approximately 7. In anotherexample, it is possible to use platinum (Pt) as the bottom electrode 26and conventional titanium nitride (TiN) as the barrier layer 32.Degradation due to high-temperature oxidizing conditions is therebyreduced.

In another embodiment, the barrier layer 32 does not exist between thedielectric 34 and the bottom electrode 26. In an additional embodiment,a barrier layer 32 does not exist between the bottom electrode 26 andthe poly plug 20.

In yet another embodiment, the environmental temperature during theplasma treatment is generally lower than in conventional approaches. Alow-temperature plasma treatment tends to reduce the time associatedwith performing a re-oxidation anneal thereby reducing manufacturingcosts and time.

Reduction of Oxygen Vacancies with Electrolysis

Another embodiment of the invention fills the oxygen vacancies with anovel electrolysis technique. FIG. 7 illustrates an electrolysis chamber70 that contains electrodes 71A and 71B, an electrolytic solution 72, awafer carrier 74 and one or more wafers 62. The wafers 62 are immersedin the electrolytic solution 72.

The electrolysis chamber 70 is a conventional chamber for the wettreatment of wafers 62. In one embodiment, the electrodes 71A and 71Bare connected to a direct current (DC) power supply the output of whichcan be varied. In one embodiment, the electric strength is set based onthe number of oxygen vacancies, the temperature of the electrolyticsolution 72, and the amount of time the wafers 62 remain in theelectrolytic solution 72. Exemplary values of the electric strength varyfrom approximately 250 kilovolts per centimeter (kV/cm) to approximately2000 kV/cm.

The electrolytic solution 72 is created by bubbling oxygen or ozone in asuitable electrolyte. The electrolyte is a conductive substance thatserves to decrease the electric resistance to enable operation of theelectrolysis with a decreased direct-current voltage. The electrolyte isprepared by dissolving an electrolytic salt such as sodium chloride(NaCl), ammonium acetate (C₂H₇NO₂), ammonium chloride (ClH₄N) or thelike into water. In other embodiments, the electrolyte is prepared bydissolving into water, alkaline compounds such as sodium hydroxide,potassium hydroxide, ammonia or the like. The concentration of theelectrolyte in the aqueous solution can vary over a wide range. In otherembodiments, however, the electrolyte is not used.

The temperature of the electrolysis chamber 70 can vary fromapproximately 20° C. to approximately 100° C. For example, in oneembodiment, dielectrics 34, 56 comprise barium strontium titanate thatis subjected to electrolysis at temperatures less than 100° C.

The electrolytic solution 72 is subjected to the bias 60 from theelectrodes 71A and 71B. Oxygen ions are then created by bubbling oxygen,ozone or nitrous oxide in the electrolytic solution 72. The DC voltagedriving the electrodes 71A and 71B generates a bias 60 having anelectric field, whereby the electrolytic solution 72 is electrolyzed.The polarity of the bias 60 is set so that the oxygen vacancies in thedielectric 34, 56 migrate towards the electrolytic solution 72. As theoxygen vacancies migrate towards the surface of the dielectric 34, 56,the oxygen ions in the electrolytic solution 72 combine with the oxygenvacancies and thereby reduce the number of oxygen vacancies in thedielectric 34, 56.

For example, after the dielectric 34 has been deposited on the bottomelectrode 26, the wafer 62 is placed in the electrolytic solution 72. Inthis example, the dielectric 34 is a BST layer that is approximately 200Å thick. Oxygen ions are created within the electrolytic solution 72 bybubbling oxygen (O₂), nitrous oxide (N₂O), or ozone (O₃) into theelectrolytic solution. A bias 60 is applied to the electrolytic solution72 that causes the oxygen vacancies in the BST layer to migrate towardsthe surface of the dielectric 34, 56 where they combine with oxygen ionsin the electrolytic solution 72. The oxygen vacancies in the dielectric34 are thereby reduced.

In another embodiment, oxygen ions are not created by bubbling oxygen,ozone or nitrous oxide in the electrolytic solution 72. Rather, themigration of the oxygen vacancies to the surface of the dielectric 34,56 combine with available oxygen ions in the electrolytic solution 72.

An advantage of one embodiment of the electrolytic treatment is that theremoval of the oxygen vacancies in the dielectric 34 does notsubstantially oxidize or degrade the poly plug 20. For example, theoxygen ions in the electrolytic solution 772 do not generally diffusethrough the barrier layer 32 or the bottom electrode 26 to significantlyoxidize or degrade the poly plug 20. For embodiments without the barrierlayer 32, the oxygen ions in the electrolytic solution 72 do notgenerally diffuse through the bottom electrode to significantly degradeor oxidize the poly plug 20. Thus, after reducing the number of oxygenvacancies in the dielectric 34, the poly plug 20 remains substantiallyfree of oxidation.

The deposited amorphous dielectric 34 can then be converted to acrystalline phase during a relatively quick high-temperature reflow. Forexample, a dielectric 34 comprising tantalum pentoxide or BST can besubjected to a rapid thermal anneal in a nitrogen (N₂) environment fromapproximately 30 to approximately 60 seconds at temperatures exceeding500° C. The rapid thermal anneal also reduces the degradation oroxidation that can occur to the poly plug 20. Thereafter, the secondconductive layer 36 is deposited on the dielectric 34.

In another example with the MIM 50, after the dielectric 56 has beendeposited on the first electrode 54, the MIM 50 is subjected to thenovel electrolysis treatment. The MIM 50 is placed in the electrolyticsolution 72. The bias 60 is applied to the MIM 50 and the oxygenvacancies migrate towards the surface of the dielectric 56 where theycombine with oxygen ions in the electrolytic solution 72. The oxygenvacancies in the dielectric 56 are thereby reduced.

An advantage of one embodiment of the electrolytic treatment is that theremoval of the oxygen vacancies in the dielectric 34 does notsubstantially oxidize or degrade the first electrode 54, the barrierlayer 32, and/or poly plug 20. For example, the oxygen ions in theplasma treatment do not generally diffuse through the dielectric 34 tosignificantly oxidize or degrade the first electrode 54, the barrierlayer 32, and/or poly plug 20. Thus, after reducing the number of oxygenvacancies in the dielectric 34, the first electrode 54, the barrierlayer 32, and/or poly plug 20 remain substantially free of oxidation.Thereafter, the second electrode 58 is deposited on the dielectric 56.

An advantage of the novel electrolysis treatment is that theelectrolytic solution 72 and the bias 60 are generally uniformthroughout the surface of the wafer 62. Thus, the electrolysis treatmentis effective at reducing oxygen vacancies that exist inthree-dimensional surfaces such as sidewalls, roughed surfaces, and thelike.

An additional advantage of one embodiment of the electrolysis treatmentis that the barrier layer 32 can be eliminated. Furthermore, theenvironmental temperature is generally lower than in conventionalhigh-temperature approaches exceeding approximately 500° C. Reducingoxygen vacancies at temperatures below approximately 100° C. reducesoxidation of the bottom electrode 26 or the poly plug 20. Likewise, inthe MIM 50, reducing oxygen vacancies at lower temperatures reduces theoxidation of the first electrode 54 and the poly plug 20.

Because there is less oxidation to the bottom electrode 26, the polyplug 20 or the first electrode 54 the total capacitance increases.Furthermore, more desirable bottom electrodes 26 and barrier layers 32can be used. For example, a bottom electrode 26 comprising nitrided HSGpolysilicon can retain its permittivity of approximately 7. In anotherexample, it is possible to use platinum (Pt) as the bottom electrode 26and conventional titanium nitride (TiN) as the barrier layer 32.Degradation due to high-temperature oxidizing conditions is therebyreduced.

In another embodiment, the barrier layer 32 does not exist between thedielectric 34 and the bottom electrode 26. In an additional embodiment,a barrier layer 32 does not exist between the bottom electrode 26 andthe poly plug 20.

In yet another embodiment, the environmental temperature during theplasma treatment is generally lower than in conventional approaches. Alow-temperature plasma treatment tends to reduce the time associatedwith performing a re-oxidation anneal thereby reducing manufacturingcosts and time.

Although the foregoing invention has been described in terms of certainpreferred embodiments, other embodiments will become apparent to thoseof ordinary skill in the art in view of the disclosure herein.Accordingly, the present invention is not intended to be limited by therecitation of preferred embodiments, but is intended to be definedsolely by reference to the appended claims.

We claim:
 1. A semiconductor structure comprising: a poly plugsubstantially free of oxidation; a first electrode above and in contactwith at least a portion of the poly plug; a biased dielectric layersubstantially free of oxygen vacancies above at least a portion of thefirst electrode, the dielectric layer having a high dielectric constant;and a second electrode above at least a portion of the dielectric layer.2. The semiconductor structure of claim 1 wherein the poly plugcomprises polysilicon.
 3. The semiconductor structure of claim 1 whereinthe poly plug comprises doped polycrystalline silicon.
 4. Thesemiconductor structure of claim 1 wherein the poly plug comprisestungsten.
 5. The semiconductor structure of claim 1 wherein the polyplug comprises aluminum.
 6. The semiconductor structure of claim 1wherein the high dielectric constant exceeds
 20. 7. The semiconductorstructure of claim 1 wherein an electric field directs oxygen vacanciestoward a surface.
 8. The semiconductor structure of claim 1 wherein thedielectric layer is subjected to a bias to direct oxygen vacanciestoward a surface.
 9. The semiconductor structure of claim 1 wherein thebiased dielectric layer is subjected to a bias comprising anelectromagnetic field, a magnetic field, a voltage, or a current. 10.The semiconductor structure of claim 1 wherein the biased dielectriclayer is placed in an electrolytic solution where the electrolyticsolution is electrolyzed by a DC voltage driving electrodes to generatea bias.
 11. A memory cell comprising: a poly plug substantially free ofoxidation; a first electrode above and in contact with at least aportion of the poly plug; a biased dielectric layer substantially freeof oxygen vacancies above at least a portion of the first electrode, thedielectric layer having a high dielectric constant; and a secondelectrode above at least a portion of the dielectric layer.
 12. Thememory cell of claim 11 wherein the poly plug comprises polysilicon. 13.The memory cell of claim 11 wherein the poly plug comprises dopedpolycrystalline silicon.
 14. The memory cell of claim 11 wherein thepoly plug comprises tungsten.
 15. The memory cell of claim 11 whereinthe poly plug comprises aluminum.
 16. The memory cell of claim 11wherein the high constant dielectric is a material selected from thegroup of tantalum pentoxide, barium strontium titanate, strontiumtitanate, barium titanate, lead zirconium titanate, strontium bismuthtantalate, or tantalum pentoxide doped with titanium silicon.
 17. Thememory cell of claim 11 wherein the high constant dielectric is between40 Å and 500 Å thick.
 18. The memory cell of claim 11 wherein the firstelectrode is a material selected from the group of hemispherical grainedsilicon, doped polysilicon, or polysilicon.
 19. The memory cell of claim11 wherein an electric field directs oxygen vacancies toward a surface.20. The memory cell of claim 11 wherein the dielectric layer issubjected to a bias to direct oxygen vacancies toward a surface.
 21. Thememory cell of claim 11 wherein the biased dielectric layer is subjectedto a bias comprising an electromagnetic field, a magnetic field, avoltage, or a current.
 22. The memory cell of claim 11 wherein thebiased dielectric layer is placed in an electrolytic solution where theelectrolytic solution is electrolyzed by a DC voltage driving electrodesto generate a bias.
 23. A metal-insulator-metal structure comprising: apoly plug substantially free of oxidation; a first metal layersubstantially free of oxidation above and in contact with at least aportion of the poly plug; a biased dielectric layer substantially freeof oxygen vacancies above and in contact with the first metal layer, thedielectric layer having a high dielectric constant; and a second metallayer above the dielectric layer.
 24. The metal-insulator-metalstructure of claim 23 wherein the first metal layer is a materialselected from the group of platinum, molybdenum, silver, ruthenium,ruthenium oxide, iridium, iridium oxide, palladium, tungsten, tungstennitride, tantalum nitride, titanium nitride, or titanium oxygen nitride.25. The metal-insulator-metal structure of claim 23 wherein the highconstant dielectric is a material selected from the group of tantalumpentoxide, barium strontium titanate, strontium titanate, bariumtitanate, lead zirconium titanate, strontium bismuth tantalate, ortantalum pentoxide doped with titanium and/or silicon.
 26. Themetal-insulator-metal structure of claim 23 wherein the second metallayer is a material selected from the group of platinum, molybdenum,silver, ruthenium, ruthenium oxide, iridium, iridium oxide, palladium,tungsten, tungsten nitride, tantalum nitride, titanium nitride ortitanium oxygen nitride.
 27. The metal-insulator-metal structure ofclaim 23 wherein an electric field directs oxygen vacancies toward asurface.
 28. The metal-insulator-metal structure of claim 23 wherein thedielectric layer is subjected to a bias to direct oxygen vacanciestoward a surface.
 29. The metal-insulator-metal structure of claim 23wherein the biased dielectric layer is subjected to a bias comprising anelectromagnetic field, a magnetic field, a voltage, or a current. 30.The metal-insulator-metal structure of claim 23 wherein the biaseddielectric layer is placed in an electrolytic solution where theelectrolytic solution is electrolyzed by a DC voltage driving electrodesto generate a bias.